We implemented this simple CNN accelerator based on the Eeyriss. The input filter size is 4x4xF where F is tunable parameters (number of filters), ranging from 8 to 32 stepsize=8. The size of the input feature map is 64圆4xI where I is tunable parameters (number of input channels) ranging from 8 to 32， stepsize=8.Though we have these assumptions in our design, it is still a general design, we can add these addresses generation part later for a real computing system. testbench_gen.py to generate all the memory footprints of the input feature map and weights, then read these files in your testbench). The input addresses generation part is omitted, thus you can assume, on each request of the input feature map and weight, the data on the input port is correct (read the testbench for more details, basically, you first using the script.The output bandwidth is 2x25 bits (maximally writing 2 outputs to main memory simultaneously).The input feature map bandwidth is 8x8 bits, and weight bandwidth is also 8x8 bits (maximally reading 8 input feature maps and 8 weights simultaneously).The bit length of all the input feature maps and weights is 8 bits, and the output is 25bits data.resource/Project_2.0.pdf, the following lists some main requests: (We use the Design Complier & VCS to compile and simulate our design) Design requirementsĭetailed requirements are under. However, you can synthesize this desing to a FPGA, since we did not use any vender sepcific verilog grammer. Rui Li: Li: The files required by the synthesis part can not be public accessed, though we have proved that it is a synthesizable design, you may not be able to reproduce the result part.
This is a simple CNN Accelerator design for the VLSI course project.
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